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Tracks

Special Tracks (TBC)

In addition to the general session, submissions are invited for the following tracks on reconfigurable computing applications and techniques.

Track on High Performance Reconfigurable Computing (HPRC)

Co-chairs

Jason Bakos, University of South Carolina, USA
Andrew Schmidt, ISI/USC, USA

Description 

Reconfigurable computing has been gaining attention in both the high-performance computing (HPC) and the high-performance embedded computing (HPEC) communities. The synergistic use of multiprocessing techniques and reconfigurable parallelism has shown orders of magnitude improvements in performance, power efficiency, and cost for many applications. Numerous emerging architectures (in-socket accelerators, tightly-coupled accelerators, homogeneous/heterogeneous Multi-processor Systems-on-Chips, embedded FPGAs, self-organizing computing substrates), techniques (dynamic/partial reconfiguration, run-time adaptability, hardware virtualization) and paradigms shifts (anti-machines, evolvable/bio-inspired systems) open new perspectives and contribute to widen the spectrum of potential benefits of reconfigurable hardware. However, widespread adoption of this technology is hampered by numerous difficulties in using the hardware and software. Both architectures and programming tools/methodologies lack the proper maturity and therefore pose severe limitations in term of usability for high-performance computing applications and high-performance embedded systems.
 
The High-Performance Reconfigurable Computing (HPRC) track at ReConFig invites submissions from researchers and developers from this field as well as application scientists and HPC/HPEC communities attempting to use this technology to implement computationally intensive applications.

Topics

  • Systems and emerging architectures
  • Dynamic Hardware reconfiguration
  • Reconfigurable instruction set/VLIW processors and MPSoC architectures
  • Run-time environments
  • Libraries, standards, and interoperability
  • Performance modeling, prediction, and benchmarks
  • Scientific and engineering applications
  • Novel FPGA architectures for HPRC

Track on Multiprocessor Systems and Networks on Chip (MPSoC)

Co-chairs

Diana Goehringer, TU Dresden, Germany
David Andrews, University of Arkansas, USA

Description

 
The end of Dennard scaling forced a paradigm shift from scalar to multiprocessor systems on chips. From high-end data center servers to IoT devices, single chip multicore processors form our fundamental computing infrastructure. Energy and latency considerations have continued to evolve multicore architectures towards systems with mixes of heterogeneous compute resources. Along this evolutionary line FPGAs have become a standard component within the suite of application accelerators available to accelerate applications. Continued increases in gate densities, the emergence of libraries of soft IP system components, as well as diffused processing and memory components have enabled FPGAs to serve as foundational silicon within which a complete heterogeneous chip multiprocessor system can be fielded.
In addition to their use along these classic evolutionary paths, FPGAs are also becoming a fundamental component within emerging memory driven and near memory computing heterogeneous multiprocessing architectures. In these systems FPGAs are expanding past their classic role as application centric custom coprocessors, to fill the missing gaps in system support not met with commodity processors and system components, hardware/software boundaries, and software protocol stacks. FPGAs are playing an important role within these systems to extend memory address ranges past the capabilities of existing ISA’s, extend operating system support for data coherency, synchronization, and security across large pools of non cached shared memory, and bridge wired and emerging optical interconnects.
The purpose of this track is to provide a venue to discuss emerging research across both evolutionary and revolutionary paths of FPGAs in multiprocessor architectures. Novel trends and uses of reconfigurable architectures across all aspects of MPSoCs are of interest. Furthermore, on-chip intercommunication continues to be a topic of high importance in this track.

 

Topics

  • Tool Adaption / Extension for handling the complexity of actual and novel architectures
  • Reconfiguration methods and solutions for on chip load balancing
  • Industrial interests: Fields of application for MPSoC architectures
  • Multilevel parallelization and hybrid concepts on hierarchical systems
  • New optimized algorithms adapted to the specific architectures
  • Numerical methods compliant with the memory hierarchy
  • Adaptive schemes on heterogeneous architectures
  • Providing powerful programming models allowing programmers to express parallelism, data access, and synchronization
  • Supporting code partitioning between hardware and software
  • Developing tools for performance analysis and debugging
  • Virtualization technology to abstract applications from the underlying multicore architecture

Track on Productivity Environments and High Level Languages (PE)

Co-chairs

Eduardo de la Torre, Technical University of Madrid, Spain
Michael Huebner, Ruhr University Bochum, Germany

Description 

Design productivity remains a significant impediment to the more widespread adoption of reconfigurable computing for many high performance computing application areas. Unlike software development environments which are characterized by high-level, rapid, and interactive development/debug flows, FPGA-based reconfigurable computing design remains a mostly batch-oriented hardware design activity relying on HDL's, RTL synthesis, and logic analyzers. However, design productivity can be enhanced in a number of ways, including: the use of high level languages and High Level Synthesis (HLS), the use of rapid prototyping CAD tool flows to reduce synthesis, place, and route times (possibly allowing for a tradeoff of tool runtime against quality of result), the use of formal methods, the use of advanced verification methodologies such as hardware-in-the-loop debug and verification, the use of emulation platforms, etc.
 
This special track seeks the latest innovations in productivity tools and approaches for reconfigurable computing, focusing on productivity and quality gain.

Topics

  • Productivity metrics and experience reports
  • Advances in HLS tools
  • Productivity gain using high level languages
  • Rapid prototyping approaches
  • Formal methods for reconfigurable computing
  • Validation improvements using high level languages
  • Rapid debugging environments
  • Late binding support in hardware
  • Model driven engineering for reconfigurable computing
  • Debugging-compliant HLS approaches
  • QoS improvements using high level languages
  • Hardware support for high level languages execution
  • Novel approaches for fast prototyping-to-deployment shift

Track on Reconfigurable Computing for Signal Processing (DSP)

Co-chairs


Sonia Lopez Alarcon, Rochester Institute of Technology, USA

Description

Modern FPGAs devices offer DSP-optimized capabilities that deliver the right balance of high-performance logic, serial connectivity and signal processing capabilities. This track welcomes submissions on all aspects of reconfigurable computing and FPGA devices applied to digital signal processing applications.
 

Topics

Topics include, but are not limited to:
  • Novel reconfigurable architectures for signal processing applications
  • Coarse-grain architectures for signal processing
  • Low-power signal processing architecture and implementation
  • Design tools for signal processing on reconfigurable platforms
  • Novel algorithms for signal processing reconfigurable platforms
  • Exploiting heterogenous resources on modern programmable logic devices for signal processing applications

Track on Reconfigurable Computing for Security and Cryptography (SC)

Co-chairs

Nele Mentens, KU Leuven, Belgium
Sylvain Guilley,TELECOM-ParisTech, France

Description 

Reconfigurable hardware offers unique opportunities for the design and implementation of secure applications in embedded and high-end computing platforms. High performance, carefully-controlled execution, and physical isolation are just a few of the advantages that hardware brings over software. At the same time, new challenges appear, such as the protection of intellectual property in a reconfigurable fabric, and the protection of soft-hardware against malicious tampering. This special track seeks the latest innovations in reconfigurable computing for security and cryptography. 

Topics

  • Hardware Implementation of Novel Cryptographic Algorithms and Protocols
  • Reconfigurable Cryptographic Primitives
  • Special-Purpose Hardware for Cryptanalysis
  • Hardware Support for Trustworthy Software Execution
  • True and Pseudo Random Generators
  • Circuit Identification and Physical Unclonable Functions
  • Efficient Methods for Protection of Hardware IPs
  • FPGA Design Security
  • Fault Attacks and Side-channel Attacks
  • Hardware Tamper Resistance and Tamper Evidence
  • Hardware Trojan Detection and Resistance
  • Design Flows for Hardware-based Secure Systems
  • Performance Evaluation of Secure Reconfigurable Hardware

Track on Reconfiguration Techniques (RT)

Co-chairs

Dirk Stroobandt, Ghent University, Belgium
Eli Bozorgzadeh, University of California Irvine, USA

Description 

FPGAs (Field-Programmable Gate Arrays) are used to accelerate a wide spectrum of applications, in embedded as well as in high-performance systems. Most current uses of FPGAs are static, where a design is programmed once and then used to execute the application. Partial and dynamic reconfiguration allows the reuse of hardware resources and possible hardware cost savings. Furthermore, by adopting dynamic reconfiguration, a system is able to accomplish virtualization, which can be used to allow portability. This track aims at providing a forum to discuss and present state-of-the-art industrial and academic experiences concerning reconfiguration techniques.

Papers with contributions to the following topics are particularly welcome:

Topics

  • Runtime support
    • Dynamic adaptation of architectures to application runtime requirements
    • Runtime mapping techniques allowed by dynamic reconfiguration
    • Operating Systems supporting reconfiguration techniques
    • Hardware virtualization
  • CAD tools and design time
    • Programming models and languages supporting reconfiguration techniques
    • Design and compilation flows for dynamically reconfigurable devices
    • Modeling, simulating and debugging dynamically reconfigured designs
    • The use of reconfiguration techniques to improve performance, to save area, to reduce energy consumption, to improve resilience, etc.
  • Architectural-related aspects
    • Bio-inspired reconfigurable computing systems
    • The use of dynamic reconfiguration techniques for prototyping circuits and systems
    • Reconfiguration techniques to deal with unreliability and to improve fault tolerance
    • Reconfiguration techniques to customize hardware resources (interconnections, functional units, buffers, multicore interconnect topologies, etc.)
  • Applications taking advantage of reconfiguration techniques
  • Teaching dynamic reconfiguration concepts

Track on Reconfigurable Computing for Networks and Communications (NC)

Co-chairs (TBC)

Description 

Reconfigurable computing offers a unique technology for networking and communications, in that it offers both programmability and performance. These characteristics are needed in data planes for Software Defined Networking (SDN) and Network Functions Virtualization (NFV), two important trends in modern networking. Design of such data planes introduces various challenges. A first challenge is delivering the required throughput, as transmission rates start to approach and exceed 100 Gbit/sec, with as little latency as possible. A second challenge is providing design flows that are accessible to networking experts, typically with a software background, by hiding low-level hardware details. A third challenge is providing standard runtime software interfaces from network software stacks to the reconfigurable hardware. This track welcomes research contributions from academia and industry that address one or more of these challenges, and of course other foundational matters such as security or virtualization.

Topics

  • Configurable hardware implementations of high-performance packet data planes
  • Tools and methodologies for applying reconfigurable computing to networking
  • Specialized accelerators for networking functions and virtual switches
  • Integration of reconfigurable computing with standard runtime APIs like DPDK, ODP, and OpenFlow.
  • Virtualized hardware coupled to software running in virtual machines
  • Management and configuration of reconfigurable networking systems
  • Security of reconfigurable systems
  • Big data stream (pre- and post-) processing
  • Near-memory computing
  • Smart reconfigurable NICs