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Tracks

Special Tracks

In addition to the general sessions, submissions are invited for the following tracks on reconfigurable computing applications and techniques.

High Performance Computing Systems and Applications

Co-chairs

Jason Bakos, University of South Carolina, USA
Andrew Schmidt, ISI/USC, USA

Description 

Reconfigurable computing has been gaining attention in both the high-performance computing (HPC) and the high-performance embedded computing (HPEC) communities. The synergistic use of multiprocessing techniques and reconfigurable parallelism has shown orders of magnitude improvements in performance, power efficiency, and cost for many applications. Numerous emerging architectures (in-socket accelerators, tightly-coupled accelerators, homogeneous/heterogeneous Multi-processor Systems-on-Chips, embedded FPGAs, self-organizing computing substrates), techniques (dynamic/partial reconfiguration, run-time adaptability, hardware virtualization) and paradigms shifts (anti-machines, evolvable/bio-inspired systems) open new perspectives and contribute to widen the spectrum of potential benefits of reconfigurable hardware. However, widespread adoption of this technology is hampered by numerous difficulties in using the hardware and software. Both architectures and programming tools/methodologies lack the proper maturity and therefore pose severe limitations in term of usability for high-performance computing applications and high-performance embedded systems.
 
The High-Performance Reconfigurable Computing (HPRC) track at ReConFig invites submissions from researchers and developers from this field as well as application scientists and HPC/HPEC communities attempting to use this technology to implement computationally intensive applications.

Topics

  • Systems and emerging architectures
  • Dynamic Hardware reconfiguration
  • Reconfigurable instruction set/VLIW processors and MPSoC architectures
  • Run-time environments
  • Libraries, standards, and interoperability
  • Performance modeling, prediction, and benchmarks
  • Scientific and engineering applications
  • Novel FPGA architectures for HPRC

Security, Cryptography, Fault Tolerance, and High Assurance

Co-chairs

Nele Mentens, KU Leuven, Belgium
Aydin Aysu, North Carolina State University, USA

Description 

Reconfigurable hardware offers unique opportunities for the design and implementation of secure applications in embedded and high-end computing platforms. High performance, carefully-controlled execution, and physical isolation are just a few of the advantages that hardware brings over software. At the same time, new challenges appear, such as the protection of intellectual property in a reconfigurable fabric, and the protection of soft-hardware against malicious tampering. This special track seeks the latest innovations in reconfigurable computing for security and cryptography. 

Topics

  • Hardware Implementation of Novel Cryptographic Algorithms and Protocols
  • Reconfigurable Cryptographic Primitives
  • Special-Purpose Hardware for Cryptanalysis
  • Hardware Support for Trustworthy Software Execution
  • True and Pseudo Random Generators
  • Circuit Identification and Physical Unclonable Functions
  • Efficient Methods for Protection of Hardware IPs
  • FPGA Design Security
  • Fault Attacks and Side-channel Attacks
  • Hardware Tamper Resistance and Tamper Evidence
  • Hardware Trojan Detection and Resistance
  • Design Flows for Hardware-based Secure Systems
  • Performance Evaluation of Secure Reconfigurable Hardware

Artificial Intelligence and Machine Learning

Co-chairs

Gabriel Wiesz, Microsoft, USA
Tinoosh Mohsenin, University of Maryland Baltimore County, USA

Description

Machine learning has redefined the decision-making and detection capabilities of computing systems, and hardware acceleration has increased the data processing capabilities of machine learning systems by orders of magnitude.

This special track seeks the latest innovations in reconfigurable computing and architectures for hardware-accelerated machine learning. covering all types of computing systems, from low-power embedded and mobile systems to data-center-scale clusters, supported by reconfigurable hardware such as FPGAs, CGRAs, or new architectures. We will accept both long and short paper submissions covering all machine learning techniques, including both training and inference, and mechanisms such as neural networks, decision trees, regression, support vector machines, mixture models, and clustering. Strong paper submissions will demonstrate experiments performed on real hardware and document any accuracy loss (or gain) achieved by the accelerated implementation against a state-of-the-art reference implementation.

Authors are invited to submit original contributions related to the following topics:
  • Novel reconfigurable architectures for deep learning and brain-inspired computing in FPGSA
  • Programmable and scalable accelerators for deep neural networks, spiking neural networks, recurrent neural networks (RNNs), deep reinforcement learning and generative adversarial networks (GANs)
  • Reconfigurable Multi-modal embedded and edge machine learning for IoT, health and wearable devices.
  • In-memory and near-memory computing architectures and implementation in FPGAs
  • Sparse computing architectures for IO and memory reductions
  • FPGA Hardware architecture and implementation for big data analytics used in data-center-scale clusters